News
Titel: New low-cost FPGA board for SoC development Date: 13.06.2006
8052 @ 30 MHz - free IP for system development

Hagenberg, Upper Austria - Successful Hpe_mini series extended with Lattice FPGA board

The development board is based on a Lattice ECP33 FPGA, which is equivalent to 300,000 ASIC gates. Interfaces include RS232, USB, Ethernet etc. Along with 256 Mb (8Mx32) of Flash, 8 Mb of SRAM (256kx32) as well as a DDR RAM socket, these fulfil all requirements demanded of a CPU development board. The Human Interface consisting of a keypad, LEDs, 7-segment display, switches and an LCD connector provide an easy interface for communicating with your own application. For more information, please refer to our homepage at http://www.ger-fae.at.

MSC offers workshops in several major cities, where persons interested can easily get a hands-on-experience with 8052 and LEON3 applications. Since all VHDL and C sources are provided on a Training CD-ROM, users can start developing right after the workshop.


Gleichmann Electronics Research has set new standards with its highly complex yet cost-efficient FPGA development boards. Complete system developments with 8-bit systems, e.g. an 8052 running at 30 MHz with 1 instruction/clock up to 32-bit systems featuring a LEON3 can be done instantly and easily with these boards. Executable applications along with source code for both processors facilitate starting your own development.
But who needs a custom microcontroller when a number of processors are available off the peg? The answer is simple: All those companies that cannot afford proclamations over and over again, all those that need custom functionality on the chip, all developers that need to directly interface to internal high-speed busses like an AMBA AHB. There are still more reasons to be found.
For all of you who do not know the LEON3 processor: The LEON3 is a SPARCV8-compliant CPU with an internal AMBA 2.0 bus system. It was originally developed by the ESA for space applications. The VHDL sources of the processor can be downloaded from the Web free of charge and can be used according to the GNU GPL. The CPU is part of the GRLIB library of IP cores by Gaisler Research. Contained within are the most common macro functions such as: UART, Ethernet, PCI, SDRAM controller. Available soon: PCI express, graphics VGA and a DDR RAM controller. The complete tool chain for development and debugging of your applications, up to real-time operating systems and Linux can be downloaded free of charge. Please contact us for more information!