News
Titel: IDE and Designer v6.2 FPGA Development Software by Actel Date: 15.07.2005



Actel is pleased to announce the release of Libero® Integrated Design Environment (IDE) and Designer v6.2 FPGA development software.

Libero IDE Gold is now FREE, replacing Libero IDE Silver. Upgrade now by registering at http://register.actel.com/RegSerial.asp and benefit from the many features of Libero IDE v6.2.

Key Features:

SmartTime Timing Environment provides new comprehensive interfaces for timing constraints and timing analysis. In addition, the industry standard Synopsys® Design Constraints (SDC) is supported. SmartTime supports ProASIC3, ProASIC3E, ProASICPLUS®, Axcelerator®, RTAX-S, SX-A, and eX devices.

Synplicity® Synplify® AE 8.1a features SDC generation plus performance improvement for ProASICPLUS, ProASIC3/E, and Axcelerator devices.

Magma® Design Automation PALACE(tm) AE 3.0 Physical Synthesis supports Axcelerator devices, providing an additional 15% (average) performance improvement. Performance is also improved for ProASIC3/E and ProASICPLUS devices.
Many other enhancements are included in Libero IDE and Designer v6.2. To learn more and view all the features of v6.2, read the "What's New" section of the Actel Software Tools website at http://www.actel.com/products/tools/sw.html.

Thank you for your interest in Actel. For more information don't hesitate to contact us: Actel@msc-ge.com