ULC – Ultimate Logic Conversion
[PDF 457KB]
ULC – Ultimate Logic Conversion
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Newsletter 6/2005: ULC – Ultimate Logic Conversion [PDF 457KB] ULC – Ultimate Logic Conversion |
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The Ultimate Cost Reduction for FPGA & CPLD Applications In today's market, cost reduction is a must in order to maintain competitiveness. FPGA and CPLD devices allow for quick design cycles, and corrections or improvements during pre-production. However, as soon as the design is finalised and volume production starts, cost and manufacturing ability becomes the most important criteria. No one wants to pay for programmability that is not required! Atmel‘s Ultimate Logic Conversion (ULC) offers a pin-to-pin drop-in replacement for your CPLD or FPGA
From the customer‘s point of view it is quite simple to do a conversion. When the CPLD or FPGA design is finished and the revision can be frozen, the final netlist – VHDL, Verilog or EDIF – is sent to Atmel to be converted into a „Structured Array“. The whole risk of conversion is on Atmel‘s side, because the customer ONLY pays when the device is functional within the application. Up to an 80% price reduction may be achieved when converting from CPLD / FPGA to Atmel‘s Structured Arrays. The below Example shows a conversion of a 256-macrocell CPLD. This 2.5ns speed version is a very expensive solution and this table shows the maximum cost reduction which can be achieved. To illustrate also the minimum cost reduction, an example has been calculated with the much cheaper standard device.
Structured Arrays are manufactured by Atmel in 0.5µ, 0.35µ; und 0.18µ technology. With the availability of these technologies, Atmel is able to convert almost all CPLD‘s and FPGA‘s from the main vendors in the market, such as Altera and Xilinx. Embedded blocks like DPRAM are part of this implementation and can be converted as well.
A conversion always makes sense when your total FPGA or CPLD solution spend is significantly higher than the NRE charge and device cost of the structured array solution. In your calculation, you also have to take into account that FPGA designs do require a configuration PROM which is not needed when converted to ULC.
The above table shows the comparison between the NRE cost of ASIC vs. Atmel ULC. As an option, Atmel also offers the ability to amortise the NRE cost across the device price for a better cost distribution. The right column show the minimum value to be ordered. What are the lead-times for a ULC conversion?
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For more information don't hesitate to contact us: Atmel@msc-ge.com |
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