Microsemi SoC

Axcelerator Family of FPGAs

High Performance System Integration

Actel_Axcelerator_logo

Actel Bildcomposition Rennfahren

The latest antifuse FPGA family offered by Actel, Axcelerator, offers high performance and unprecedented design security at densities of up to 2 million equivalent system gates. Based upon the Actel AX architecture, Axcelerator has several system-level features, such as embedded SRAM (with embedded FIFO control logic), PLLs, segmentable clocks, chip-wide highway routing, and carry logic. Based upon 0.15 µ, seven-layers-of-metal CMOS antifuse process technology, Axcelerator offers a level of performance previously only available in ASIC technology.

Actel Bildcomposition Axelerator

  • 350 MHz system performance
  • 500+ MHz internal performance
  • 500+ MHz embedded FIFOs
  • PLL output up to 1 GHz and 8 PLLs per device
  • 6 levels of logic at 156+ MHz
  • 1.5 V, 1.8 V, 2.5 V, and 3.3 V mixed-voltage operation
  • 8 I/O banks per device
  • 8 global clocks per device
  • 4.5 kbits variable-aspect RAM blocks with built-in FIFO control
  • Intelligent low-power operation
  • Secure programming technology prevents reverse engineering and design theft

space

AX125

AX250

AX500

AX1000

AX2000

System Gates

125,000

250,000

500,000

1000,000

2,000,000

Dedicated Registers

672

1,408

2,688

6,048

10,752

Max Registers (core)

1,344

2,816

5,376

12,096

21,504

Embedded RAM bits

18,432

55,296

73,728

165,888

64

Embedded RAM Blocks (4,608bits)

4

12

16

36

88

Max User I/Os

168

248

336

516

684

Max. Number of LVDS Pairs

84

124

168

258

342

PLLs

8

8

8

8

8

GLobal Clocks

8

8

8

8

8

Packages

CS180

PQ208

PQ208

FG256

FG256

FG324

FG484

FG484

FG484

FG876

FG676

FG896

FG896

FG1152

BG729