AVR32 UC3 Processor Family

The AVR32 UC series is based on a 3-stage pipeline Harvard architecture and includes advanced features such as DSP arithmetic’s, single-cycle multiply and accumulate instructions and atomic bit or word read-modify-write instruction.

The AVR32 UC core is the first core in the industry to integrate single-cycle read/write SRAM with a direct interface to the CPU that bypasses the system bus to achieve faster execution, cycle deterministic and low power consumption.

The core can deliver up to 1.3 Dhrystone MIPS/MHz running from on-chip memory

Features :

• Hazardless 3-stage pipeline Harvard architecture
• Fixed point DSP arithmetic & single-cycle MAC
• Hardware division
• Tightly coupled on-chip SRAM
• Modeless 16-bit & 32-bit instruction set
• Atomic data manipulation
• Low latency nested interrupt
• Non-maskable interrupt (NMI)
• Memory protection unit (MPU)
• Powerful emulation system including real-time trace

• Lowest Power Consumption
• More MHz per mW
• Dynamic Power Management

• Higher Performance
• More work per clock cycle
• High speed data transfers
• Unrivalled DSP performance

• Shortest time to market
• AVR32 Software Framework
• High quality development tools
• Experienced tech support staff

AVR32 UC3 Product Series

The UC3 controller products are available in three families:

UC3 controllers with Ethernet MAC and external bus interface (EBI):  AVR32 UC3A Family UC3 Controller with low-pin count: AVR32 UC3B Family UC3 Controller in low power technology with CAT and PWM AVR UC3L Family