
ProASIC®3/E
The Low-Power, Low-Cost FPGA Solution
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The ProASIC3 series of flash FPGAs offers a breakthrough in power, price, performance, density, and features for today’s most demanding high-volume applications. ProASIC3 devices support the ARM Cortex-M1 processor, offering the benefits of programmability and time-to-market at low cost. ProASIC3 devices are based on nonvolatile flash technology and support 15,000 to 3,000,000 gates and up to 620 high-performance I/Os.
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ProASIC3/E Devices |
A3P015 |
A3P030 |
A3P060 |
A3P125 |
A3P250 |
A3P400 |
A3P600 |
A3P1000 |
A3PE600 |
A3PE1500 |
A3PE3000 |
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Cortex-M1 Devices |
M1A3P250 |
M1A3P400 |
M1A3P600 |
M1A3P1000 |
M1A3PE1500 |
M1A3PE3000 |
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System Gates |
15,000 |
30,000 |
60,000 |
125,000 |
250,000 |
400,000 |
600,000 |
1,000,000 |
600,000 |
1,500,000 |
3,000,000 |
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Typical Equivalent |
128 |
256 |
512 |
1,024 |
2,048 |
- |
- |
- |
- |
- |
- |
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VersaTiles (D-flip-flops) |
384 |
768 |
1,536 |
3,072 |
6,144 |
9,216 |
13,824 |
24,576 |
13,824 |
38,400 |
75,264 |
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RAM kbits (1,024 bits) |
- |
- |
18 |
36 |
36 |
54 |
108 |
144 |
108 |
270 |
504 |
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4,608-Bit Blocks |
- |
- |
4 |
8 |
8 |
12 |
24 |
32 |
24 |
60 |
112 |
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FlashROM Bits |
1,000 |
1,000 |
1,000 |
1,000 |
1,000 |
1,000 |
1,000 |
1,000 |
1,000 |
1,000 |
1,000 |
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Secure (AES) ISP1 |
- |
- |
Yes |
Yes |
Yes |
Yes |
Yes |
Yes |
Yes |
Yes |
Yes |
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Intergrated PLLs with CCC |
- |
- |
1 |
1 |
1 |
1 |
1 |
1 |
6 |
6 |
6 |
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VersaNet Globals |
6 |
6 |
18 |
18 |
18 |
18 |
18 |
18 |
18 |
18 |
18 |
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I/O Banks |
2 |
2 |
2 |
2 |
4 |
4 |
4 |
4 |
8 |
8 |
8 |
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Maximum User I/Os |
49 |
81 |
96 |
133 |
157 |
194 |
235 |
300 |
270 |
444 |
620 |
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Package Pins |
QN48 | ||||||||||
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QN68 |
QN68 | ||||||||||
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QN132 |
QN132 |
QN132 |
QN132 ² | ||||||||
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VQ100 |
VQ100 |
VQ100 |
VQ100 | ||||||||
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TQ144 |
TQ144 | ||||||||||
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PQ208 |
PQ208 |
PQ208 |
PQ208 |
PQ208 |
PQ208 |
PQ208 |
PQ208 |
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FG144 |
FG144 |
FG144 |
FG144 |
FG144 |
FG144 | ||||||
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FG256 ² |
FG256 |
FG256 |
FG256 |
FG256 | |||||||
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FG324 |
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FG484 |
FG484 |
FG484 |
FG484 |
FG484 |
FG484 |
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FG676 | |||||||||||
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FG896 |
1 AES is not available for Cortex-M1 ProASIC3 devices.
2 The M1A3P250 device does not support this package.
ProASIC®3 nano
The Lowest Cost Solution with Enhanced I/O Capabilities
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Actel’s innovative ProASIC3 nano devices bring a new level of value and flexibility to high volume markets. When measured against the typical project metrics of performance, cost, flexibility and time-to-market, ProASIC3 nano devices provide an attractive alternative to ASICs and application-specific standard products (ASSPs) in fast moving or highly competitive markets. Customer-driven total system cost reduction was a key design criteria for the ProASIC3 nano program. Reduced device cost, availability of known good die, a single chip implementation, and a broad selection of small footprint packages, all contribute to lower total system costs. |
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ProASIC3 nano Devices |
A3PN010 |
A3PN015 |
A3PN020 |
A3PN030 |
A3PN060 |
A3PN125 |
A3PN250 |
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System Gates |
10,000 |
15,000 |
20,000 |
30,000 |
60,000 |
125,000 |
250,000 |
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Typical Equivalent Macrocells |
86 |
128 |
172 |
256 |
512 |
1,024 |
2,048 |
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VersaTiles (D-flip-flops) |
260 |
384 |
520 |
768 |
1,536 |
3,072 |
6,144 |
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RAM kbits (1,024 bits) |
- |
- |
- |
- |
18 |
36 |
36 |
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4,608-Bit Blocks |
- |
- |
- |
- |
4 |
8 |
8 |
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FlashROM Bits |
1,000 |
1,000 |
1,000 |
1,000 |
1,000 |
1,000 |
1,000 |
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Secure (AES) ISP |
- |
- |
- |
- |
Yes |
Yes |
Yes |
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Integrated PLLs with CCC |
- |
- |
- |
- |
1 |
1 |
1 |
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VersaNet Globals |
4 |
4 |
4 |
6 |
18 |
18 |
18 |
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I/O Banks |
2 |
3 |
3 |
2 |
2 |
2 |
4 |
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Maximum User I/Os |
34 |
49 |
52 |
81 |
71 |
71 |
68 |
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Known Good Die User I/Os |
34 |
- |
52 |
83 |
71 |
71 |
68 |
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Package Pins |
QN48 |
QN48 | |||||
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QN68 |
QN68 |
QN68 | |||||
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VQ100 |
VQ100 |
VQ100 |
VQ100 |
ProASIC3 Starter Kit
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ProASIC®3L
Balancing Low Power, Performance, and Low Cost
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ProASIC3L FPGAs feature 40 percent lower dynamic power and 90 percent lower static power than the previous generation ProASIC3 FPGAs and orders of magnitude lower power than SRAM competitors, combining dramatically reduced power consumption with up to 350 MHz operation. The ProASIC3L family also supports the free implementation of an FPGA-optimized 32-bit ARM Cortex-M1 processor, enabling system designers to select the Actel flash FPGA solution that best meets their speed and power design equirements, regardless of application or volume. Optimized software tools using power-driven layout (PDL) provide instant power reduction capabilities. |
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* AES is not available for Cortex-M1 ProASIC3L devices. |
Cortex-M1 ProASIC3 Development Kit
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ProASIC®3 for Automotive
From Concept to Production
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Actel’s T-Grade Automotive ProASIC3 FPGAs offer Grade 2 (TA =105°C / TJ=115°C) and Grade 1 (TA=125°C / TJ=135°C) AECQ100-qualified devices. With densities up to 1 M system gates, the Automotive ProASIC3 T-Grade FPGA is the only FPGA solution offering 135°C junction temperature on a high-density, feature-rich FPGA. ProASIC3 T-Grade devices deliver an optimal combination of high reliability, neutron immunity, features and density to powertrain, safety, telematics, and infotainment applications. In addition to AECQ100 qualification and a TS 16949 certified Quality Management System, Actel offers PPAP documentation on ProASIC3 T-Grade devices. Based on our popular ProASIC3 flash product offerings, T-Grade Automotive ProASIC3 FPGAs provide four new choices for advanced automotive systems.
All packages available in RoHS-compliant and standard leaded packages. |




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