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Microsemi SoC

ProASIC®3/E

The Low-Power, Low-Cost FPGA Solution

ProASIC3/3E

The ProASIC3 series of flash FPGAs offers a breakthrough in power, price, performance, density, and features for today’s most demanding high-volume applications. ProASIC3 devices support the ARM Cortex-M1 processor, offering the benefits of programmability and time-to-market at low cost. ProASIC3 devices are based on nonvolatile flash technology and support 15,000 to 3,000,000 gates and up to 620 high-performance I/Os.

  • Single chip, single voltage 
  • Nonvolatile
  • Reprogrammable
  • Live at power-up
  • Maximum design security
  • Ultra-low power
  • Firm-error immune
  • Clock management
  • Advanced I/O standards
  • User nonvolatile FlashROM
  • Secure ISP
  • High performance

ProASIC3/E Devices

A3P015

A3P030

A3P060

A3P125

A3P250

A3P400

A3P600

A3P1000

A3PE600

A3PE1500

A3PE3000

Cortex-M1 Devices

M1A3P250

M1A3P400

M1A3P600

M1A3P1000

M1A3PE1500

M1A3PE3000

System Gates

15,000

30,000

60,000

125,000

250,000

400,000

600,000

1,000,000

600,000

1,500,000

3,000,000

Typical Equivalent
Macrocells

128

256

512

1,024

2,048

-

-

-

-

-

-

VersaTiles (D-flip-flops)

384

768

1,536

3,072

6,144

9,216

13,824

24,576

13,824

38,400

75,264

RAM kbits (1,024 bits)

-

-

18

36

36

54

108

144

108

270

504

4,608-Bit Blocks

-

-

4

8

8

12

24

32

24

60

112

FlashROM Bits

1,000

1,000

1,000

1,000

1,000

1,000

1,000

1,000

1,000

1,000

1,000

Secure (AES) ISP1

-

-

Yes

Yes

Yes

Yes

Yes

Yes

Yes

Yes

Yes

Intergrated PLLs with CCC

-

-

1

1

1

1

1

1

6

6

6

VersaNet Globals

6

6

18

18

18

18

18

18

18

18

18

I/O Banks

2

2

2

2

4

4

4

4

8

8

8

Maximum User I/Os

49

81

96

133

157

194

235

300

270

444

620


Package Pins

QN48

QN68

QN68

QN132

QN132

QN132

QN132 ²

VQ100

VQ100

VQ100

VQ100

TQ144

TQ144

PQ208

PQ208

PQ208

PQ208

PQ208

PQ208

PQ208

PQ208

FG144

FG144

FG144

FG144

FG144

FG144

FG256 ²

FG256

FG256

FG256

FG256

FG324

FG484

FG484

FG484

FG484

FG484

FG484

FG676

FG896

1 AES is not available for Cortex-M1 ProASIC3 devices.
2 The M1A3P250 device does not support this package.

ProASIC®3 nano

The Lowest Cost Solution with Enhanced I/O Capabilities

Actel’s innovative ProASIC3 nano devices bring a new level of value and flexibility to high volume markets. When measured against the typical project metrics of performance, cost, flexibility and time-to-market, ProASIC3 nano devices provide an attractive alternative to ASICs and application-specific standard products (ASSPs) in fast moving or highly competitive markets. Customer-driven total system cost reduction was a key design criteria for the ProASIC3 nano program. Reduced device cost, availability of known good die, a single chip implementation, and a broad selection of small footprint packages, all contribute to lower total system costs.

  • 1.5 V core for low power
  • Known good die supported
  • 350 MHz system performance
  • Embedded SRAM NVM
  • Firm-error immune
  • Enhanced commercial temperature
  • Enhanced I/O features
  • ISP and security
  • Reprogrammable flash technology
  • Zero lead time on selected devices
  • CCCs and PLLs

ProASIC3 nano Devices

A3PN010

A3PN015

A3PN020

A3PN030

A3PN060

A3PN125

A3PN250

System Gates

10,000

15,000

20,000

30,000

60,000

125,000

250,000

Typical Equivalent Macrocells

86

128

172

256

512

1,024

2,048

VersaTiles (D-flip-flops)

260

384

520

768

1,536

3,072

6,144

RAM kbits (1,024 bits)

-

-

-

-

18

36

36

4,608-Bit Blocks

-

-

-

-

4

8

8

FlashROM Bits

1,000

1,000

1,000

1,000

1,000

1,000

1,000

Secure (AES) ISP

-

-

-

-

Yes

Yes

Yes

Integrated PLLs with CCC

-

-

-

-

1

1

1

VersaNet Globals

4

4

4

6

18

18

18

I/O Banks

2

3

3

2

2

2

4

Maximum User I/Os

34

49

52

81

71

71

68

Known Good Die User I/Os

34

-

52

83

71

71

68


Package Pins

QN48

QN48

QN68

QN68

QN68

VQ100

VQ100

VQ100

VQ100

ProASIC3 Starter Kit

ProASIC3StarterKit
  • Evaluation board with an A3PE1500-PQ208 silicon device
  • Eight I/O banks for ProASIC3E (six for ProASIC3): two can be independently set to 1.5 V, 1.8 V, 2.5 V, or 3.3 V (one for ProASIC3);four are fixed at 3.3 V (applies to ProASIC3); and two are fixed at 2.5 V (applies to ProASIC3E).
  • Clocks: Oscillator for system clock and manual clock option are provided
  • Eight LEDs and four switches provide simple inputs and outputs to the system.
  • LCD display module
  • Two CAT5E RJ45 connectors for high-speed LVDS communications
  • Two programming headers support in-system programming (ISP) of single and JTAG-chained boards using FlashPro3
  • FlashPro3 programmer
  • Free one-year Libero IDE Gold license and software
  • Web download of Libero IDE software CD
  • User’s guide and Libero IDE tutorial
  • PCB schematics and layout files
  • Example designs

ProASIC®3L

Balancing Low Power, Performance, and Low Cost

ProASIC3L FPGAs feature 40 percent lower dynamic power and 90 percent lower static power than the previous generation ProASIC3 FPGAs and orders of magnitude lower power than SRAM competitors, combining dramatically reduced power consumption with up to 350 MHz operation. The ProASIC3L family also supports the free implementation of an FPGA-optimized 32-bit ARM Cortex-M1 processor, enabling system designers to select the Actel flash FPGA solution that best meets their speed and power design equirements, regardless of application or volume. Optimized software tools using power-driven layout (PDL) provide instant power reduction capabilities.

  • Low power 1.2 V to 1.5 V core operation
  • 700 Mbps DDR, LVDS capable I/Os
  • Up to 350 MHz system performance
  • Enhanced I/O features
  • Embedded SRAM and NVM
  • Firm-error immune
  • ISP and security
  • Flash*Freeze technology for lowest power
  • Reprogrammable flash technology
  • CCCs and PLLs

ProASIC3L Devices

A3P250L

A3P600L

A3P1000L

A3PE3000L

Cortex-M1 Devices

M1A3P600L

M1A3P1000L

M1A3PE3000L

System Gates

250,000

600,000

1,000,000

3,000,000

VersaTiles (D-flip-flops)

6,144

13,824

24,576

75,264

RAM kbits (1,024 bits)

36

108

144

504

4,608-Bit Blocks

8

24

32

113

FlashROM Bits

1,000

1,000

1,000

1,000

Secure (AES) ISP*

Yes

Yes

Yes

Yes

Integrated PLLs with CCC

1

1

1

6

VersaNet Globals

18

18

18

18

I/O Banks

4

4

4

8

Maximum User I/Os

157

235

300

620


Package Pins

VQ100

PQ208

PQ208

PQ208

PQ208

FG144

FG144

FG144

FG256

FG256

FG256

FG324

FG484

FG484

FG484

FG896

* AES is not available for Cortex-M1 ProASIC3L devices.

Cortex-M1 ProASIC3 Development Kit

Cortex-M1 ProASIC3 Development Kit
  • Oscillator for system clock is provided
  • Eight LEDs and eight switches provide simple inputs and outputs to the system.
  • USB programming and debug connection
  • Second USB connection for USB-to-serial (RS232) interface
  • Optional board power connector for an external supply, but none is needed when connected to an USB cable
  • Memory devices
  • 1 MB of SRAM provided on board
  • 16 MB of flash memory provided on board
  • General purpose I/O banks – Three 40-pin GPIO banks are provided for interfacing to other equipment. Two of these banks are fully populated.
  • FlashPro3 programmer built into board
  • Power supply
  • Free one-year Libero IDE Gold license and software
  • Web download of Libero IDE software CD
  • User’s guide and Libero IDE tutorial
  • PCB schematics and layout files
  • Example designs

ProASIC®3 for Automotive

From Concept to Production

actel proasic airbag

actel proasic antrieb

actel proasic motor

Actel’s T-Grade Automotive ProASIC3 FPGAs offer Grade 2 (TA =105°C / TJ=115°C) and Grade 1 (TA=125°C / TJ=135°C) AECQ100-qualified devices. With densities up to 1 M system gates, the Automotive ProASIC3 T-Grade FPGA is the only FPGA solution offering 135°C junction temperature on a high-density, feature-rich FPGA. ProASIC3 T-Grade devices deliver an optimal combination of high reliability, neutron immunity, features and density to powertrain, safety, telematics, and infotainment applications.

In addition to AECQ100 qualification and a TS 16949 certified Quality Management System, Actel offers PPAP documentation on ProASIC3 T-Grade devices.

Based on our popular ProASIC3 flash product offerings, T-Grade Automotive ProASIC3 FPGAs provide four new choices for advanced automotive systems.

  • AEC-Q100 Compliant
  • Two standard offerings:
    • Grade 2: –40°C to 105°C ambient with absolute maximum junction 115°C
    • Grade 1: –40°C to 125°C ambient with absolute maximum junction 135°C
  • 100% temperature testing
  • Burn-in an available option
  • Leaded and unleaded packages offered

ProASIC3 T-Grade

 A3P060

A3P125

A3P250

A3P1000

System Gates

60 k

125 k

250 k

1 M

Embedded RAM Bits

18 k

36 k

36 k

144 k

Embedded RAM Blocks
(4,608-bit blocks)

4

8

8

32

Maximum User I/Os
(Std+/LVDS)

96

97

157/38

300/74

Packages

VQ100

VQ100

VQ100

FG144

FG144

FG144

FG144

QN132

QN132

FG256

FG256

FG484

All packages available in RoHS-compliant and standard leaded packages.

Contacts

webshopkorb webshop

MSC Webshop ToolguideA3P-Products