MachXO2
The Do-it-All PLD for Low Density Applications
The MachXO2 family of infinitely reconfigurable Programmable Logic Devices (PLDs) offers designers of low density PLDs an unprecedented mix of low cost, low power and high system integration in a single device. Combining an optimized look-up table (LUT) architecture with 65-nm embedded Flash process technology, the MachXO2 family delivers a 3X increase in logic density, a 10X increase in embedded memory, more than a 100X reduction in static power and up to 30% lower cost compared to the prior generation MachXO PLD family. In addition, the MachXO2 family includes hardened implementations of some of the most popular functions used in system applications (telecom infrastructure, computing, high end industrial, high end medical) and consumer applications (smart phones, GPS devices, mobile computing, digital cameras). These include User Flash Memory (UFM), I²C, SPI and timer/counter. Thus, through the provision of these features and capabilities, the MachXO2 family offers designers a "Do-it-All PLD" for low density applications.
Key Features & Benefits
MachXO2 PLD
|
Feature |
Benefit |
|---|---|
|
Instant-on, non-volatile |
Powers up in less than 1ms enabling precise control during system boot-up |
|
Single chip |
No external configuration memory required resulting in high security and low total system cost |
| Low power |
Increases battery life and helps reduce the overall system power |
| Hardened I2C, SPI, and timer/counter |
Minimizes the use of LUTs for implementing additional functionality |
|
On-chip User Flash Memory (UFM) |
Provides up to 256Kbits of general purpose Flash memory |
|
Embedded & distributed memory |
Efficient data buffering and resource usage |
| Robust PLLs and on board oscillator |
Integrated clock management reducing total system cost |
|
Flexible, high performance I/Os |
Interfaces with multiple voltages, DDR/DDR2/LPDDR memory and 7:1 LVDS interfaces |
|
TransFR technology and dual boot |
Allows remote and reliable field upgrades while the equipment operates |
| Device TraceID and One Time Programmability (OTP) |
Prevents further erasure or programming of the Flash; unique 64bit TraceID can be used for device tracking purposes |
To maximize design flexibility, the MachXO2 family is offered in three options:
MachXO2 Device Options
|
Focus |
Option |
Regulator |
Nominal Vcc (V) | Internal Vcc (V) | System Performance (MHz) |
|---|---|---|---|---|---|
|
Low Power |
ZE |
1,2 |
1,2 |
60 |
|
|
High Performance |
HC |
x |
3,3; 2,5 |
1,2 |
150 |
|
High Performance |
HE |
1,2 |
1,2 |
150 |
Device Selection Guide
MachXO2 PLD Family Selection Guide
|
LCMXO2-256 |
LCMXO2-640 |
LCMXO2-1200 |
LCMXO2-2000 |
LCMXO2-4000 |
LCMXO2-7000 |
|
|---|---|---|---|---|---|---|
|
Density LUTs |
256 |
640 |
1280 |
2112 |
4320 |
6864 |
|
Density Macrocells*1 |
128 |
320 |
640 |
1056 |
2160 |
3432 |
|
EBR RAM (Kbits) |
0 |
18 |
64 |
74 |
92 |
240 |
|
Dist. SRAM (Kbits) |
2 |
5 |
10 |
16 |
34 |
54 |
|
User Flash Memory (Kbits) |
0 |
24 |
64 |
80 |
96 |
256 |
|
PLL |
0 |
0 |
1 |
1 |
2 |
2 |
Package |
I/O |
|||||
|
25-ball WLCSP (2.5x2.5 mm)*2 |
18 | |||||
|
36-ball WLCSP (3.1x3.1 mm)*2 |
29 | |||||
|
64-ball @cBGA (4x4 mm) |
45 | |||||
|
100-pin TQFP (14x14 mm) |
56 |
79 |
80 |
80 | ||
|
132-ball csBGA (8x8 mm) |
56 |
80 |
105 |
105 |
105 | |
|
144-pin TQFP (20x20 mm) |
108 |
112 |
115 |
115 |
||
|
256-ball caBGA (14x14 mm) |
207 |
207 |
207 |
|||
|
256-ball ftBGA (17x17 mm) |
207 |
207 |
207 |
|||
|
332-ball caBGA (17x17 mm) |
275 |
279 |
||||
|
324-ball ftBGA (19x19 mm) |
279 |
335 |
||||
|
Typical Static Power |
||||||
|
ZE (uW) |
19 |
33 |
70 |
98 |
153 |
230 |
|
HC (mW) |
4 |
7 |
13 |
18 |
32 |
48 |
|
HE (mW) |
2 |
3 |
5 |
|||
*1 Assumes 1 macrocell = 2 LUTs
*2 Contact your Lattice sales representative for the support of WLCSP packages
Free Design Tools to Accelerate Your Development Time
Start designing with MachXO2 devices today using freely downloadable Lattice Diamond software or alternatively, the free ispLEVER Starter software with an installed control pack. Accelerate your development time with a comprehensive set of popular free reference designs for functions commonly used in system and consumer applications and optimized for the MachXO2 PLD family. In addition, two development kits that speed up the evaluation of MachXO2 devices will be made available soon.
